Known means of recovering digital signals from a radio signal which has been frequency modulated by the digital signal include direct conversion receivers, in which the last stage of conversion is to a baseband signal rather than to a low frequency signal, as in more conventional receivers. In a direct conversion receiver, the baseband signal is amplified and filtered, and then demodulated by analog signal analysis, using digital signal processing techniques. In a more conventional receiver, amplification and filtering is provided in two or more conversion stages and a discriminator circuit is used for demodulation. The use of a direct conversion approach lends itself more readily to a more integrated receiver having fewer integrated circuits.
DC offset is problematic in a direct conversion receiver, in which the mixer output is generally DC coupled through the baseband filter and amplifier(s). This DC coupling is required in order to provide an integrated circuit which does not require the addition of either large onchip capacitors or pads to off-chip capacitors. DC offset is caused by local oscillator (LO) to radio frequency (RF) leakage in the baseband converting mixer and transistor mismatch in a mixer and the baseband filter. The DC offset in combination with large DC gain can cause the baseband filter to exceed its dynamic range. For example, in a receiver running off a one volt supply a typical maximum baseband filter signal is 200 millivolts (mV) peak to peak. With a baseband amplifier gain of 70 decibels (dB), a DC offset greater than approximately 63 microvolts (uV) at the input of the baseband amplifier will overload the baseband filter. Mixer output offset due to LO to RF leakage and transistor mismatch can exceed 2 mV, which is much greater than the allowable 63 uV.
A past approach to resolving the DC offset problem has been to wrap a DC offset correction circuit around the amplifier, which establishes a low corner frequency (alternatively described as the highpass frequency) for the baseband signal, below which the bandpass signal is significantly attenuated (e.g., 70 decibels). The low corner frequency must be low enough to allow reliable recovery of the baseband signal for all anticipated combinations of data. In the well known FLEX.TM. protocol, when operating at 4800 bits per second, the required low corner frequency is less than 100 Hertz (Hz). A large capacitor has been used in such DC offset correction circuits to attain this low corner frequency. The settling time of such a circuit is on the order of 50 milliseconds. Providing for such a long settling time can impact pager battery life and scan time in roaming pagers. An improvement used in some data receivers is to provide two highpass corner frequencies, e.g., 100 Hz and 1 KiloHertz (KHz), and switch from the higher frequency to the lower frequency after synchronization is completed. Such an approach requires the switching of capacitors or transconductance and introduces a rapid change of bandwidth. The rapid change of bandwidth typically causes a similar effect as a DC offset, which also slows the response time.
Thus, what is needed is a means to provide a DC offset correction in a direct conversion receiver while at the same time having a fast response time,